1. Field of the Invention
This invention relates to an analog-to-digital (A/D) converter and more particularly to an oversampled, multiple order modulation portion of the A/D converter. The converter performs noise shaping with minimal signal-to-noise (S/N) degradation over a wide range of input levels.
2. Description of the Relevant Art
Oversampled A/D converters, often denoted as "delta-sigma converters" are well known in the art. Delta-sigma converters have gained in popularity due primarily to their high resolution output and adaptability to mixed-signal VLSI processes. The delta-sigma converter is inherently an oversampling converter, although oversampling is just one of the techniques contributing to the its overall performance. A delta-sigma converter essentially digitizes an analog signal at a very high sampling rate (oversampling) to perform a noise-shaping function. Digital filtering after noise-shaping allows the delta-sigma converter to achieve a higher effective resolution than the analog input signal. Decimation is thereafter used to reduce the effective sampling rate back to the "Nyquist" rate. To gain an understanding of delta-sigma converters it is important to understand the operation of oversampling, noise-shaping, digital filtering and decimation.
FIG. 1 illustrates a conventional second order delta-sigma converter 10. Converter 10 is denoted a second order delta-sigma converter in that an error signal at output Y is integrated twice with respect to time. Accordingly, converter 10 comprises two integrator circuits 12 shown in dashed line. Integrators 12 are connected in series between a first summing node 14 and a quantizer 16. Quantizer 16 (shown as a digitizing analog-to-digital, or "a/d", block) quantizes the analog output signal from the second integrator 12 and produces a digital code at output Y. The quantized output is fed back through a digital-to-analog (denoted as "d/a") converter 18 to amplifiers, denoted in FIG. 1 as having respective gain scaling factors g.sub.0 and g.sub.1. The outputs of the amplifiers are connected to first summing node 14 as well as second summing node 20.
Output signal Y is fed as digital code to a digital decimation filter 22. Filter 22 functions to filter out quantization noise produced by quantizer 16 and to decimate the sampling frequency back to the original Nyquist rate. Digital filtering is fairly well known, and includes a low pass technique utilizing a finite impulse response (FIR) filter, infinite impulse response (IIR) filter, or a combination of both. Decimation can be included with or separate from the filter. Decimation is incorporated with the filter if the filter output is digitally resampled at a lower rate than the quantizer sampling frequency. In the latter instance, it may not be necessary to compute a filter output for every input sample thereby achieving considerable efficiency in the computational process.
Inclusion of feedback from the digital-to-analog circuit 18 to the first and second nodes 14 and 20, respectively, provides stability to the overall architecture. Circuit 18, the output of which is coupled either directly or through amplifiers to nodes 14 and 20 via feedback, basically functions as a reference voltage selector. Either a positive or a negative reference voltage (either +Vref or -Vref) is selected by circuit 18 in accordance with its receipt of a high logic level or low logic level, respectively. Selector 18 thereby forwards an appropriate reference voltage to summing nodes 14 and 20 in accordance with the corresponding logic value of digital output signal Y.
Conventional delta-sigma modulators often cannot convert a full-range of analog input voltages. As shown in FIG. 2, as the analog input signal X approaches full scale (i.e., 0.0 dB), noise is injected into the feedback loop due to the non-linear behavior of quantizer 16. Specifically, as the input signal X approaches peak value, quantizer 16, which is essentially a comparator with gain, begins to enter a non-linear state. Non-linearity is caused primarily from an increase in quantizer 16 input while reference feedback levels output from circuit 18 remains fixed. That is, the gain of quantizer 16 comparator undergoes non-linear operation relative to fixed output and input level increases. A non-linear response at high input values causes the feedback loop to operate in what is often called an "overload" condition. Overload is defined herein as a property of a delta-sigma converter resulting from failure of the quantized output data to follow increases in analog input values through negative feedback. As quantizer 16 input is increased, the quantizer gain will appear smaller due to its limited output levels (.+-.Vref). At some input level exceeding a threshold overload amount, linear operation of delta-sigma converter cannot be maintained, causing a degradation of signal-to-noise (S/N) ratio. FIG. 2 illustrates a relatively linear slope 24 which changes to a non-linear slope 26 as the input level is increased toward full scale or peak values. Overload of the feedback loop is illustrated at the point (approximately -6.0 dB) in which linear slope 24 converts to a substantially non-linear curvature 26.
Reduction in comparator gain from a linear model to a non-linear model not only injects unacceptable noise into the feedback loop during peak voltages of the input signal, but it also can cause overall instability of a delta-sigma converter even after the input signal which caused the instability is removed. Many skilled artisans have utilized a reset trigger at the integrator circuits which resets converter operation if loop instability occurs. In addition to, or in lieu of the reset trigger, gain scaling the first order integrator has also been used. Gain scaling the feedback reference voltages to a level above the peak analog input values has been looked to as a way in which to avoid overload by utilizing lower signals within the integrator and quantizer. A description of gain scaling applicable to a first or second order, single stage delta-sigma converter is provided in reference to U.S. Pat. No. 4,851,841 (herein incorporated by reference).
Gain scaling the effective feedback reference voltage to a level exceeding the analog input voltage allows S/N boosting of the converted analog input signal near the extremes of the input signal peak values. Gain scaling the effective feedback reference voltage is illustrated in reference to the following transfer function of output signal Y, indicative of the single loop, second order delta-sigma converter of FIG. 1: EQU Y=XZ.sup.-2 /g.sub.0 +Q(1-Z.sup.-1).sup.2 (Eq. 1).
where Z.sup.-2 represents two delay period associated with blocks d of both integrators 12, 1-Z.sup.-1 represents the transfer function of each integrator 12, and g.sub.0 represents the scaling factor of the first order amplifier. After decimation, Dout is represented as the following transfer function: EQU Dout=Yg.sub.0 =XZ.sup.-2 +Q(1-Z.sup.-1).sup.-2 g.sub.0 (Eq. 2)
If noise is present within the analog input signal, then an analog noise factor appears in equation 2. Application of gain g.sub.0 to the analog input will cause an increase in the analog noise factor as well as increase in the quantization noise factor Q(1-Z.sup.-1).sup.-2. Presence of gain scaling factor g.sub.o is therefore beneficial in avoiding overload but at the expense of increased quantization noise and/or analog noise forwarded to the digital output signal Dout.
Modern day delta-sigma converters attempt to minimize overload by utilizing what is often called a cascaded arrangement. A cascaded delta-sigma converter is defined as a converter having more than one stage of single or multiple-order integrators coupled together. FIG. 3 illustrates a second order stage 30 coupled in cascade with a subsequent first order stage 32 to form a cascaded 2:1 delta-sigma converter 33. Coupled between second order stage 30 and first order stage 32 is an interstage summing node 34. Summing node 34 is configured to receive a scaled down analog signal from amplifier 36 and a selectively amplified analog output from amplifier 38. The scaling of amplifier 36 can be designed having a scaling coefficient which is an inverse product of scaling coefficients within amplifiers 40a and 40b. Additionally, amplifier 38 can be designed to receive programmable instructions which define an amplification coefficient which allows interstage summing node 34 to produce (i) only analog data (i.e., data at input of quantizer 16) from first stage 30 absent quantized noise, (ii) only the quantized noise absent analog data from first stage 30, or (iii) a combination of data and noise.
Amplifier 42 at the output from interstage summing node is preferably configured with a scaling factor less than one. As a result, the level of data, noise, or both, applied to the input of the subsequent stage 32 is maintained at a level necessary to minimize overload of stage 32. Reducing the input level to the second stage causes the second stage, namely the second integrator and associated quantizer 44, to operate in a more linear range. Even if the first stage utilizes its entire dynamic range, the level of signal forwarded from amplifier 42 is maintained at a relatively low level so as not to exceed the feedback voltage levels sent by reference voltage selector (i.e., digital-to-analog converter) 46.
FIG. 4 illustrates a noise cancellation circuit 50 designed to receive the digital outputs Y.sub.1 and Y.sub.2 at each respective output of stages 30 and 32. A delay circuit 52 is coupled to receive output Y.sub.1. Delay circuit 52 functions to time delay data of Y.sub.1 relative to data of Y.sub.2, as presented to summing node 54. A quantized, differentiated signal Y.sub.2 is produced at the output of differentiator unit 60. Differentiator unit 60 comprises two series-connected digital differentiators, which in a manner known in the art, differentiates the digital difference signal from summing node 62. The output from digital differentiator 60 is added via summing node 54 to the output of delay circuit 52 as digital code at output Y. Digital signal Y represents a digital code of a high-speed digital bit pattern forwarded at the same frequency at which the quantizer circuits 16 and 44 are clocked. The relative number of logic 1s to logic 0s output by signal Y is indicative of the polarity and voltage magnitude of analog input signal X.
The form and function of cascaded 2:1 delta-sigma converter 33 and associated noise cancellation circuit 50 of FIGS. 3 and 4 are described in reference to U.S. Pat. Nos. 5,148,166 and 4,920,544 (herein incorporated by reference). As described in each of the above U.S. Patents, at least two reasons for implementing a cascaded arrangement, with appropriate noise cancellation, are to remove the quantizing noise generated by the first stage 30 and to increase noise shaping orders for the quantization noise of the second stage. Scaling the output of the interstage summing node 34, alleviates overload problems generally associated with many non-cascaded configurations. The cascaded configuration thereby achieves the advantages associated with gain scaling the first order input of the first stage. Unfortunately, however, the aforesaid cascaded arrangement by itself cannot completely eliminate overload during times in which the input analog signal X is at or near full scale values.
FIGS. 5 and 6 illustrate a cascaded 2:2 delta-sigma converter 70 with associated noise cancellation circuit 72. Converter 70 is similar to the cascaded 2:1 delta-sigma converter 31 of FIG. 4; however, converter 70 includes, within the second stage 74, two integrators instead of one. The second order second stage 74 is therefore similar to the second order first stage 76. Shown with similar reference numeral to that of FIG. 3, interstage summing node 34 includes amplifiers 36 and 38 which input a scaled signal to summing node 34. An output amplification is carried out by amplifier 42, preferably at a scaling factor less than 1, and in many instances, less than 1/2. The quantized signals Y.sub.1 and Y.sub.2 are fed into noise cancellation circuit 72 shown in FIG. 6, with delay circuit 52, summing node 54 and differentiator 60 shown with like reference numerals to that of FIG. 4.
The combination of converter 70 and noise cancellation circuit 72 produces the following transfer characteristic at output signal Y: EQU Y=XZ.sup.-4 +(1-Z.sup.-1).sup.4 Q.sub.2 /hc1 (Eq. 3),
where Z.sup.-1 represents four delay periods associated with blocks 78 and 80 of FIG. 5 and dual delay circuit 52 of FIG. 6. 1-Z.sup.-1 represents a first order noise shaping function within converter 70; Q.sub.2 represents the quantization noise introduced by quantizer 44; and, hc1 represents the gain scaling factor of amplifier 42 (interstage summing node 34 output). Quantization noise introduced by quantizer 16 is eliminated by use of noise cancellation circuit 72. The gain scaling coefficient (or factor) of amplifier 42 is denoted as hc1. The transfer functions of delay circuits associated with integrators and the integrators themselves are of common knowledge to a skilled artisan and set forth in the U.S. Pat. No. 5,061,928 (herein incorporated by reference).
Overload performance of a cascaded loop such as a 2:1, or 2:2 cascaded arrangement, is generally better than a non-cascaded, single loop. Accordingly, the arrangement shown in FIGS. 3 and 5 provide a significant improvement over the arrangement shown in FIG. 1. A cascaded converter performs over a wider dynamic range regardless of a whether the first stage is overloaded, provided the latter (second) stage is not overloaded. Any overloaded quantization noise of the first stage will be cancelled by the noise cancellation circuit 50 or 72. In order to minimize the possibility of overloading the second stage, the gain scaling factor (hc1) of amplifier 42 is made very small, preferably less than 1, and in many instances less than 1/2. By making the gain scaling factor small, overload is minimized, however, at the expense of S/N ratio. The transfer function for the digital output signal Y of equation 3 bears this result. FIG. 7 illustrates S/N plotted as a function of input level for a cascaded 2:1 arrangement, such as that shown in FIG. 3. A reduction in interstage gain scaling indicates an improvement in overload performance, but at the expense of a lower S/N ratio. For example, an interstage gain scaling of hc1=1/8 results in a linear range closer to full scale (0.0 dB) than the other, larger gain scaling factors. However, a gain scaling factor of 1/8 produces a lower S/N than the other gain scaling factors. By gain scaling the analog input voltage with a gain scaling factor g.sub.0, similar to that described in U.S. Pat. No. 4,851,841, for a cascaded 2:1 arrangement, the transfer function of output signal Y is as follows: EQU Y=XZ.sup.-3 /g.sub.0 +(1-Z.sup.-1).sup.3 Q.sub.2 /hc1 (Eq. 4)
After decimation and gain compensation of g.sub.0, the decimator output Dout will be as follows: EQU Dout=g.sub.0 Y=XZ.sup.-3 +g.sub.0 (1-Z.sup.-1).sup.3 Q.sub.2 /hc1(Eq. 5)
Adding magnitude to the input gain scaling factor g.sub.0, adds to the quantization noise factor. As such, equation 5 illustrates the negative effect of g.sub.0 upon S/N ratio.
In an attempt to offset the S/N degradation associated with a fractional interstage gain scaling, a cascaded 2:2 converter 70 can be employed having the response shown in FIG. 8. Similar to FIG. 7, FIG. 8 represents a simulated output response of signal Y for various input levels of signal X. FIG. 8 indicates an improvement in overload performance with corresponding decrease in interstage gain scaling hc1, yet at the expense of S/N ratio. A comparison of FIG. 8 to FIG. 7 illustrates an advantage in using a cascaded 2:2 arrangement. Specifically, a cascaded 2:2 converter achieves significantly higher S/N ratios for a given interstage gain scaling factor. Given a smaller interstage gain scaling factor, a cascaded 2:2 arrangement can achieve better overload performance. For example, the cascaded 2:2 architecture indicates in FIG. 8 a linear roll-off (i.e., overload) at -2.0 dB input level when configured with a 1/8 interstage scaling factor. While S/N and overload performance is significantly improved in a cascaded 2:2 arrangement, overload nonetheless still remains near input peak values.
Regardless of the delta-sigma configuration, whether it is a single stage with input gain scaling, a cascaded 2:1 modulator with interstage gain scaling and noise cancellation, or a cascaded 2:2 converter with interstage gain scaling and noise cancellation, the result remains the same: a converter which overloads at analog input voltages approaching the peak or full scale value. FIGS. 2, 7 and 8 all shown overload prior to input signal X achieving full scale. For example, if the analog input value reaches a voltage substantially near the reference voltage, a conventional converter will change from a linear operation to a non-linear operation. To further clarify, using an exemplary +3.0 v. Vref and -3.0 v. Vref feedback level, an analog input level approaching the peak voltages (e.g., exceeding in absolute value .+-.2.9 v.) of Vref will cause the converter to experience an overload condition regardless of the converter configuration. Attempts to alleviate the overload by gain scaling the feedback Vref voltage or fractionally scaling the interstage gain merely reduces the S/N ratio as a trade off to improved overload performance. It would be desirable to further enhance overload performance but not to the detriment of S/N ratio. Thus, improvements to conventional converters entail a configuration which does not enter overload prior to the analog input signal achieving peak value. Of further importance is the desire for a configuration which maintains a high S/N ratio throughout the dynamic range of the converter, having an input signal which can extend up to and possibly beyond the peak value level of the feedback reference voltages.